`define DELAY(N, clk) begin \
	repeat(N) @(posedge clk);\
	#1ps;\
end

module testbench();

//-------------------------------------{{{common cfg
timeunit 1ns;
timeprecision 1ps;
initial $timeformat(-9,3,"ns",6);

string tc_name;
int tc_seed;

initial begin
  if(!$value$plusargs("tc_name=%s", tc_name)) $error("no tc_name!");
  else $display("tc name = %0s", tc_name);
  if(!$value$plusargs("ntb_random_seed=%0d", tc_seed)) $error("no tc_seed");
  else $display("tc seed = %0d", tc_seed);
end
//-------------------------------------}}}

//-------------------------------------{{{parameter declare
//-------------------------------------}}}

//-------------------------------------{{{signal declare
logic clk, rst_n;

logic [2 -1:0] sys_cfg_mode;
logic [20 -1:0] sys_cfg_kernel_size;
logic [3 -1:0] sys_cfg_stride;
logic [3 -1:0] sys_cfg_cfg_info0_layer_field0;
logic [3 -1:0] sys_cfg_cfg_info0_layer_field1;
logic [3 -1:0] sys_cfg_cfg_info0_layer_field2;
logic [3 -1:0] sys_cfg_cfg_info0_layer_field3;
logic [3 -1:0] sys_cfg_cfg_info0_layer_field4;
logic [3 -1:0] sys_cfg_cfg_info0_layer_field5;
logic [3 -1:0] sys_cfg_cfg_info1_layer_field0;
logic [3 -1:0] sys_cfg_cfg_info1_layer_field1;
logic [3 -1:0] sys_cfg_cfg_info1_layer_field2;
logic [3 -1:0] sys_cfg_cfg_info1_layer_field3;
logic [3 -1:0] sys_cfg_cfg_info1_layer_field4;
logic [3 -1:0] sys_cfg_cfg_info1_layer_field5;
logic [3 -1:0] sys_cfg_cfg_info2_layer_field0;
logic [3 -1:0] sys_cfg_cfg_info2_layer_field1;
logic [3 -1:0] sys_cfg_cfg_info2_layer_field2;
logic [3 -1:0] sys_cfg_cfg_info2_layer_field3;
logic [3 -1:0] sys_cfg_cfg_info2_layer_field4;
logic [3 -1:0] sys_cfg_cfg_info2_layer_field5;
logic [3 -1:0] sys_cfg_cfg_info3_layer_field0;
logic [3 -1:0] sys_cfg_cfg_info3_layer_field1;
logic [3 -1:0] sys_cfg_cfg_info3_layer_field2;
logic [3 -1:0] sys_cfg_cfg_info3_layer_field3;
logic [3 -1:0] sys_cfg_cfg_info3_layer_field4;
logic [3 -1:0] sys_cfg_cfg_info3_layer_field5;
logic [3 -1:0] sys_cfg_cfg_info4_layer_field0;
logic [3 -1:0] sys_cfg_cfg_info4_layer_field1;
logic [3 -1:0] sys_cfg_cfg_info4_layer_field2;
logic [3 -1:0] sys_cfg_cfg_info4_layer_field3;
logic [3 -1:0] sys_cfg_cfg_info4_layer_field4;
logic [3 -1:0] sys_cfg_cfg_info4_layer_field5;
logic [3 -1:0] sys_cfg_cfg_info5_layer_field0;
logic [3 -1:0] sys_cfg_cfg_info5_layer_field1;
logic [3 -1:0] sys_cfg_cfg_info5_layer_field2;
logic [3 -1:0] sys_cfg_cfg_info5_layer_field3;
logic [3 -1:0] sys_cfg_cfg_info5_layer_field4;
logic [3 -1:0] sys_cfg_cfg_info5_layer_field5;
logic [3 -1:0] sys_cfg_cfg_info6_layer_field0;
logic [3 -1:0] sys_cfg_cfg_info6_layer_field1;
logic [3 -1:0] sys_cfg_cfg_info6_layer_field2;
logic [3 -1:0] sys_cfg_cfg_info6_layer_field3;
logic [3 -1:0] sys_cfg_cfg_info6_layer_field4;
logic [3 -1:0] sys_cfg_cfg_info6_layer_field5;
logic [3 -1:0] sys_cfg_cfg_info7_layer_field0;
logic [3 -1:0] sys_cfg_cfg_info7_layer_field1;
logic [3 -1:0] sys_cfg_cfg_info7_layer_field2;
logic [3 -1:0] sys_cfg_cfg_info7_layer_field3;
logic [3 -1:0] sys_cfg_cfg_info7_layer_field4;
logic [3 -1:0] sys_cfg_cfg_info7_layer_field5;
logic [3 -1:0] sys_cfg_cal_mode;
logic [3 -1:0] sys_cfg_cal_round;
logic [3 -1:0] sys_cfg_cvt_mode;
logic [2 -1:0] sys_status_mode;
logic [20 -1:0] sys_status_kernel_size;
logic [3 -1:0] sys_status_stride;
logic  sys_status_blk0_status;
logic  sys_status_blk1_status;
logic  sys_status_blk2_status;
logic  sys_status_blk3_status;
logic  sys_status_blk4_status;
logic  sys_irq_resp_err_in;
logic  sys_irq_resp_err_wen;
logic  sys_irq_timeout_in;
logic  sys_irq_timeout_wen;
logic  sys_irq_inner_err_in;
logic  sys_irq_inner_err_wen;
logic  pclk;
logic  presetn;
logic [`VMM_RAL_ADDR_WIDTH     -1:0] paddr;
logic  psel;
logic  penable;
logic  pwrite;
logic [`VMM_RAL_DATA_WIDTH     -1:0] pwdata;
logic [(`VMM_RAL_DATA_WIDTH/8) -1:0] pstrb;
logic  pready;
logic [`VMM_RAL_DATA_WIDTH     -1:0] prdata;
logic  pslverr;
//-------------------------------------}}}

//-------------------------------------{{{clk/rst cfg
initial forever #5ns clk = ~clk;
initial begin
  rst_n = 1'b0;
  `DELAY(30, clk);
  rst_n = 1'b1;
end

bit sim_start; //valid/data drive while sim_start is HIGH
bit sim_finish;//sim_finish is HIGH, then #1000ns $finish, or #100000ns $finish from begin
bit sim_finish_ff, sim_finish_pulse;//use sim_finish_pulse to do something
initial begin
  sim_start  = 1'b0;
  sim_finish = 1'b0;
  `DELAY(50, clk);
end

always @(posedge clk or negedge rst_n)begin
  if(!rst_n) sim_finish_ff <= 1'b0;
  else       sim_finish_ff <= sim_finish;
end
assign sim_finish_pulse = sim_finish && !sim_finish_ff;

initial begin
  fork
  #100000ns $finish; //fork0
  begin              //fork1
    wait(sim_finish == 1'b1);
    #1000ns $finish;
  end
  join_none
end
//-------------------------------------}}}

//-------------------------------------{{{valid sig assign
//-------------------------------------}}}

//-------------------------------------{{{ready sig assign
//-------------------------------------}}}

//-------------------------------------{{{data  sig assign
//-------------------------------------}}}

//-------------------------------------{{{other sig assign
initial begin
  sys_status_mode = $urandom;
  sys_status_kernel_size = $urandom;
  sys_status_stride = $urandom;
  sys_status_blk0_status = $urandom;
  sys_status_blk1_status = $urandom;
  sys_status_blk2_status = $urandom;
  sys_status_blk3_status = $urandom;
  sys_status_blk4_status = $urandom;
  sys_irq_resp_err_in = $urandom;
  sys_irq_resp_err_wen = $urandom;
  sys_irq_timeout_in = $urandom;
  sys_irq_timeout_wen = $urandom;
  sys_irq_inner_err_in = $urandom;
  sys_irq_inner_err_wen = $urandom;
  pclk = $urandom;
  presetn = $urandom;
  paddr = $urandom;
  psel = $urandom;
  penable = $urandom;
  pwrite = $urandom;
  pwdata = $urandom;
  pstrb = $urandom;
  `DELAY(50, clk);
end

//-------------------------------------}}}

//-------------------------------------{{{rtl inst
REG_PRJ_reg_top u_REG_PRJ_reg_top(
    .sys_cfg_mode(sys_cfg_mode),
    .sys_cfg_kernel_size(sys_cfg_kernel_size),
    .sys_cfg_stride(sys_cfg_stride),
    .sys_cfg_cfg_info0_layer_field0(sys_cfg_cfg_info0_layer_field0),
    .sys_cfg_cfg_info0_layer_field1(sys_cfg_cfg_info0_layer_field1),
    .sys_cfg_cfg_info0_layer_field2(sys_cfg_cfg_info0_layer_field2),
    .sys_cfg_cfg_info0_layer_field3(sys_cfg_cfg_info0_layer_field3),
    .sys_cfg_cfg_info0_layer_field4(sys_cfg_cfg_info0_layer_field4),
    .sys_cfg_cfg_info0_layer_field5(sys_cfg_cfg_info0_layer_field5),
    .sys_cfg_cfg_info1_layer_field0(sys_cfg_cfg_info1_layer_field0),
    .sys_cfg_cfg_info1_layer_field1(sys_cfg_cfg_info1_layer_field1),
    .sys_cfg_cfg_info1_layer_field2(sys_cfg_cfg_info1_layer_field2),
    .sys_cfg_cfg_info1_layer_field3(sys_cfg_cfg_info1_layer_field3),
    .sys_cfg_cfg_info1_layer_field4(sys_cfg_cfg_info1_layer_field4),
    .sys_cfg_cfg_info1_layer_field5(sys_cfg_cfg_info1_layer_field5),
    .sys_cfg_cfg_info2_layer_field0(sys_cfg_cfg_info2_layer_field0),
    .sys_cfg_cfg_info2_layer_field1(sys_cfg_cfg_info2_layer_field1),
    .sys_cfg_cfg_info2_layer_field2(sys_cfg_cfg_info2_layer_field2),
    .sys_cfg_cfg_info2_layer_field3(sys_cfg_cfg_info2_layer_field3),
    .sys_cfg_cfg_info2_layer_field4(sys_cfg_cfg_info2_layer_field4),
    .sys_cfg_cfg_info2_layer_field5(sys_cfg_cfg_info2_layer_field5),
    .sys_cfg_cfg_info3_layer_field0(sys_cfg_cfg_info3_layer_field0),
    .sys_cfg_cfg_info3_layer_field1(sys_cfg_cfg_info3_layer_field1),
    .sys_cfg_cfg_info3_layer_field2(sys_cfg_cfg_info3_layer_field2),
    .sys_cfg_cfg_info3_layer_field3(sys_cfg_cfg_info3_layer_field3),
    .sys_cfg_cfg_info3_layer_field4(sys_cfg_cfg_info3_layer_field4),
    .sys_cfg_cfg_info3_layer_field5(sys_cfg_cfg_info3_layer_field5),
    .sys_cfg_cfg_info4_layer_field0(sys_cfg_cfg_info4_layer_field0),
    .sys_cfg_cfg_info4_layer_field1(sys_cfg_cfg_info4_layer_field1),
    .sys_cfg_cfg_info4_layer_field2(sys_cfg_cfg_info4_layer_field2),
    .sys_cfg_cfg_info4_layer_field3(sys_cfg_cfg_info4_layer_field3),
    .sys_cfg_cfg_info4_layer_field4(sys_cfg_cfg_info4_layer_field4),
    .sys_cfg_cfg_info4_layer_field5(sys_cfg_cfg_info4_layer_field5),
    .sys_cfg_cfg_info5_layer_field0(sys_cfg_cfg_info5_layer_field0),
    .sys_cfg_cfg_info5_layer_field1(sys_cfg_cfg_info5_layer_field1),
    .sys_cfg_cfg_info5_layer_field2(sys_cfg_cfg_info5_layer_field2),
    .sys_cfg_cfg_info5_layer_field3(sys_cfg_cfg_info5_layer_field3),
    .sys_cfg_cfg_info5_layer_field4(sys_cfg_cfg_info5_layer_field4),
    .sys_cfg_cfg_info5_layer_field5(sys_cfg_cfg_info5_layer_field5),
    .sys_cfg_cfg_info6_layer_field0(sys_cfg_cfg_info6_layer_field0),
    .sys_cfg_cfg_info6_layer_field1(sys_cfg_cfg_info6_layer_field1),
    .sys_cfg_cfg_info6_layer_field2(sys_cfg_cfg_info6_layer_field2),
    .sys_cfg_cfg_info6_layer_field3(sys_cfg_cfg_info6_layer_field3),
    .sys_cfg_cfg_info6_layer_field4(sys_cfg_cfg_info6_layer_field4),
    .sys_cfg_cfg_info6_layer_field5(sys_cfg_cfg_info6_layer_field5),
    .sys_cfg_cfg_info7_layer_field0(sys_cfg_cfg_info7_layer_field0),
    .sys_cfg_cfg_info7_layer_field1(sys_cfg_cfg_info7_layer_field1),
    .sys_cfg_cfg_info7_layer_field2(sys_cfg_cfg_info7_layer_field2),
    .sys_cfg_cfg_info7_layer_field3(sys_cfg_cfg_info7_layer_field3),
    .sys_cfg_cfg_info7_layer_field4(sys_cfg_cfg_info7_layer_field4),
    .sys_cfg_cfg_info7_layer_field5(sys_cfg_cfg_info7_layer_field5),
    .sys_cfg_cal_mode(sys_cfg_cal_mode),
    .sys_cfg_cal_round(sys_cfg_cal_round),
    .sys_cfg_cvt_mode(sys_cfg_cvt_mode),
    .sys_status_mode(sys_status_mode),
    .sys_status_kernel_size(sys_status_kernel_size),
    .sys_status_stride(sys_status_stride),
    .sys_status_blk0_status(sys_status_blk0_status),
    .sys_status_blk1_status(sys_status_blk1_status),
    .sys_status_blk2_status(sys_status_blk2_status),
    .sys_status_blk3_status(sys_status_blk3_status),
    .sys_status_blk4_status(sys_status_blk4_status),
    .sys_irq_resp_err_in(sys_irq_resp_err_in),
    .sys_irq_resp_err_wen(sys_irq_resp_err_wen),
    .sys_irq_timeout_in(sys_irq_timeout_in),
    .sys_irq_timeout_wen(sys_irq_timeout_wen),
    .sys_irq_inner_err_in(sys_irq_inner_err_in),
    .sys_irq_inner_err_wen(sys_irq_inner_err_wen),
    .pclk(pclk),
    .presetn(presetn),
    .paddr(paddr),
    .psel(psel),
    .penable(penable),
    .pwrite(pwrite),
    .pwdata(pwdata),
    .pstrb(pstrb),
    .pready(pready),
    .prdata(prdata),
    .pslverr(pslverr)
);

//-------------------------------------}}}

endmodule
